1. Field of the Disclosure
The present disclosure generally relates to processors and, more particularly, to prefetching at a processor.
2. Description of the Related Art
Processor architectures typically employ a memory hierarchy having external memory at the lowest level of the memory hierarchy and a cache at each higher level of the memory hierarchy. The processor architectures further employ a processor core that requests data (instructions or operand data) from the highest level cache in the memory hierarchy. In response to determining that information responsive to an access request is not stored at a particular cache in the memory hierarchy, the cache will issue an access request for the information from the cache at the next lower level in hierarchy. Some processor architectures employ non-blocking caches, whereby the caches are able to service access requests while awaiting the satisfaction of pending access requests to lower levels in the memory hierarchy. Such architectures can use a miss address buffer (MAB) to store address and other information for each pending access request. Each cache in the memory hierarchy is assigned slots of the MAB, such that the number of slots assigned to a cache governs the maximum permissible number of pending access requests for the cache.
Access requests can be of at least two types: demand requests, representing a request from the processor core for either instructions or data known to be needed by the processor; and prefetch requests that speculatively request instructions or data expected to be responsive to instructions or data references predicted to be executed at a later point. Demand requests are typically given greater priority for reservation of storage locations at the MAB. This prioritization can negatively impact prefetching due to lack of available storage locations at the MAB, thereby reducing processor efficiency.
The use of the same reference symbols in different drawings indicates similar or identical items.